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| author | Zeger Van de Vannet <747627+zegervdv@users.noreply.github.com> | 2021-12-24 23:07:56 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-12-24 17:07:56 -0500 |
| commit | eae2dc441adaf2757d7d7c9c19d4a2b389545ef3 (patch) | |
| tree | 0b8e8dbff65539f92fbfc6a479d7e2be1befd75e | |
| parent | docs: update server_configurations.md (diff) | |
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feat: add verible configuration (#1605)
| -rw-r--r-- | lua/lspconfig/server_configurations/verible.lua | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/lua/lspconfig/server_configurations/verible.lua b/lua/lspconfig/server_configurations/verible.lua new file mode 100644 index 00000000..3c4823a8 --- /dev/null +++ b/lua/lspconfig/server_configurations/verible.lua @@ -0,0 +1,21 @@ +local util = require 'lspconfig.util' + +return { + default_config = { + cmd = { 'verible-verilog-ls' }, + filetypes = { 'systemverilog', 'verilog' }, + root_dir = util.find_git_ancestor, + }, + docs = { + description = [[ +https://github.com/chipsalliance/verible + +A linter and formatter for verilog and SystemVerilog files. + +Release binaries can be downloaded from [here](https://github.com/chipsalliance/verible/releases) +and placed in a directory on PATH. + +See https://github.com/chipsalliance/verible/tree/master/verilog/tools/ls/README.md for options. + ]], + }, +} |
